1. Field of the Invention
The present invention relates to a chip for a multi-chip semiconductor device having a marking for alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same.
2. Background of the Art
In recent years, semiconductor chips (hereinafter referred to as simply “chips”) having very large scale integrated circuit (VLSI) are frequently employed for forming critical portions in computers and communication equipments. The conformation of forming a stacked body of a plurality of chips is often employed among the usage of such chips. Here, when a plurality of chip is employed to form a stacked body, the particularly critical point may be how the positions of the respective chips are adjusted, or namely the method for the alignment.
Following methods for establishing an alignment in the multiple-chip stacked semiconductor device are known.
Japanese Patent Laid-Open No. H10-303,364 (1998) discloses a method for establishing an alignment of chips, in which through holes of free of embedded material or through holes having a transparent material embedded therein are provided in the respective chips for forming the multi-layered stacked body, the through holes are irradiated with a laser beam from the lower direction and the irradiating laser beam is received by a photodetector that is provided at an upper side, and then the respective chips are moved so that the maximum intensity of the transmitted light are obtained to achieve the alignment of the upper and the lower chips.
Japanese Patent Laid-Open No. 2000-228,487 also discloses a method for establishing an alignment of chips, in which markings are drawn by using a printer or a laser marker on the backside of the chips that are flip chip-bonded in a face down orientation when the multi-chip module having a chip-on-chip structure is manufactured, and then the markings are employed as markings for achieving an alignment.
Japanese Patent Laid-Open No. 2000-228,488 also discloses a method for establishing an alignment of chips, in which electrode markings are drawn on the backside of the chips that are flip chip-bonded in a face down orientation, corresponding to the positions of the electrodes on the surfaces of the chips, when the multi-chip module having a chip-on-chip structure is manufactured, and then the markings are employed as markings for achieving an alignment.
Japanese Patent Laid-Open No. 2001-217,387 also discloses a method for establishing an alignment of chips, in which markings for alignment are provided at corresponding positions of the surfaces of respective two chips that will be joined to form a chip-on-chip structure and then the markings are employed as markings for achieving an alignment.
Japanese Patent Laid-Open No. 2002-76,247 also discloses a method for establishing an alignment of chips, in which hollow dummy vias having a diameter that are consecutively decreased from the top-arranged chip to the bottom-arranged chip, and the centers of the dummy vias of respective layers are aligned to achieve the alignment of the upper and the lower chips.